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toshiba toshiba corporation 1 tlcs-90 series tmp90c400/401 the information contained here is subject to change without notice. the information contained herein is presented only as guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. these toshiba products are intended for usage in general electronic equipments (of?e equipment, communication equipment, measuring equipment, domestic electri?ation, etc.) please make sure that you consult with us before you use these toshiba products in equip- ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traf? signal, combustion control, all types of safety devices, etc.). toshiba cannot accept liability to any damage which may occur in case these toshiba products were used in the mentioned equipments without prior consultation with toshiba. cmos 8?it microcontrollers TMP90C400N/tmp90c401n tmp90c400f/tmp90c401f 1. outline and characteristics the tmp90c400 is a high-speed advanced 8-bit microcontroller applicable to a variety of equipment. with its 8-bit cpu, rom, ram, timer/event counter and gen- eral-purpose serial interface integrated into a single cmos chip, the tmp90c400 allows the expansion of external memories for programs and data (up to 60k bytes). the tmp90c401 is the same as the tmp90c400 but without rom. the TMP90C400N/401n is in a shrink dual inline package (sdip64-p-750). the tmp90c400f/401f is in a quad flat package (qfp64-p-1420a) the characteristics of the tmp90c400 include: (1) powerful instructions: 163 basic instructions, including multiplication, division, 16-bit arithmetic operations, bit manipulation instructions (2) minimum instruction executing time: 320ns (at 12.5mhz oscillation frequency) (3) internal rom: 4k bytes (the tmp90c401 does not have a built-in rom) (4) internal ram: 128 bytes (5) memory expansion external memory: 60k bytes (6) general-purpose serial interface (1 channel) asynchronous mode, i/o interface mode (7) 8-bit timers (4 channel): (2 external clock inputs) (8) port with zero-cross detection circuit (4 inputs) (9) input/output ports (56 pins) - ports with programmable pull-up resistor (22 pins) - allows i/o selection on bit basis - multiplexer ports of address data bus (10) interrupt function: 7 internal interrupts and 3 external interrupts (11) micro direct memory access (dma) function (8 channels) (12) standby function (4 halt modes)
2 toshiba corporation tmp90c400/401 figure 1. tmp90c400 block diagram
toshiba corporation 3 tmp90c400/401 2. pin assignment and functions this section describes the assignment of input/output pins, their names and functions. 2.1 pin assignment figure 2.1 (1) shows pin assignment of the TMP90C400N/ 401n. figure 2.1 (1). pin assignment (shrink dual inline package)
4 toshiba corporation tmp90c400/401 figure 2.1 (2) shows pin assignment of the tmp90c400f/401f. figure 2.1 (2). pin assignment (flat package)
toshiba corporation 5 tmp90c400/401 2.2 pin names and functions the names of input/output pins and their functions are summa- rized in table 2.2. table 2.2 pin names and functions (1/2) pin name no. of pins i/o 3 states function p00 ~ p07 /ad0 ~ ad7 8 i/o port 0: 8-bit i/o port that allows selection of input/output on byte basis 3 states address/data bus: functions as 8-bit bidirectional address/data bus for external memory (for 401, fixed to address/data bus) p10 ~ p17 /a8 ~ a15 8 i/o port 1: 8-bit i/o port that allows selection on byte basis output address bus: functions as address bus (upper 8 bits) by ext1 set for external memory (for 401, fixed to address bus p20 ~ p23 4 i/o port 20 ~ 23: 4-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis p24 /nmi 1 i/o port 24: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis input non-maskable interrupt request pin: falling edge interrupt register pin p25 /w ait 1 i/o port 25: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis input wait: input pin for connecting slow speed memory of peripheral lsi p26 /rd 1 output port 26: 1-bit output port output read: generates strobe signal for reading external memory (for 401, fixed to rd ) p27 /wr 1 output port 27: 1-bit output port output write: generates strobe signal for writing into external memory (for 401, fixed to wr ) p30 /into 1 i/o port 30: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis input interrupt request pin 0: interrupt request pin (level/rising edge is programmable) p31 /int1 1 input port 31: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis interrupt request pin 1: rising edge interrupt request pin p32 /ti0 1 i/o port 32: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis input timer input 0: counter input pin for timer 0
6 toshiba corporation tmp90c400/401 table 2.2 pin names and functions (2/2) pin name no. of pins i/o 3 states function p33 /ti2 1 i/o port 33: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis input timer input 2: counter input pin for timer 2 p34 /t01 1 i/o port 34: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis input timer input: output of timer 0 or 1 p35 /rxd 1 i/o port 35: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis p36 /sclk 1 i/o port 36: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis output serial clock output p37 txd 1 i/o port 37: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis output transmitter serial data p40 ~ p47 8 i/o port 4: 8-bit i/o port that allows i/o selection on bit basis p50 ~ p57 8 i/o port 5: 1-bit i/o port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis p60 ~ p67 8 i/o port 6: 8-bit i/o port that allows i/o selection on bit basis ale 1 output address latch enable signal: the negative edge ale supplies an address latch timing on ad0 ~ a07 for external memory ea 1 input external access: connects with v cc pin in the tmp90c400 using internal rom, and with gnd pin in the tmp90c401 with no internal rom clk 1 output clock output: generates clock pulse at 1/4 frequency of clock oscillation. it is pulled up i nternally during resetting. reset 1 input reset: initializes the tmp90c400/401 (built-in pull-up resistor) x1/x2 2 input/output pin for quartz crystal or ceramic resonator (1 ~ 12.5mhz) v cc 1 power supply (+5v) v ss 1 ground (0v)
toshiba corporation 7 tmp90c400/401 3. operation this chapter describes the functions and the basic operations of the tmp90c400/401 in every block. the following is a description of tmp90c400 which can also be applied to tmp90c401, if not speci?ally de?ed otherwise. 3.1 cpu the tmp90c400 includes a high performance 8-bit cpu. for the function of the cpu, see the book tlcs series cpu core architecture concerning cpu operation. this chapter explains exclusively the functions of the cpu of tmp90c400 which are not described in th that book. 3.1.1 reset the basic timing of the reset operation is indicated in figure 3.1 (1). in order to reset the tmp90c400, the reset input must be maintained at the ??level for at least ten system clock cycles (10 stated: 2 m sec at 10mhz) within an operating voltage band and with a stable oscillation. when a reset request is accepted, all i/o ports function as input ports (high impedance state). the p26 (rd ), p27 (wr ) and clk pins that always function as output pins turn to the ??level. the dedicated input ports remain unchanged. the registers of the cpu also remain unchanged. note, however, that the program counter pc, the interrupt enable ?g iff are cleared to ?? register a shows an unde?ed status. when the reset is cleared, the cpu starts executing instructions from the address 0000h.
8 toshiba corporation tmp90c400/401 figure 3.1 (1a). tmp90c400 reset timing * p20 ~ p25, p30 ~ p37 and p50 ~ p57, which have programmable pull-up resistors, remain ?igh?while resetting, unless input ?ow?
toshiba corporation 9 tmp90c400/401 figure 3.1 (1b). tmp90c401 reset timing 3.1.2 exf (exchange flag) for tmp90c400, ?xf? which is inverted when the command ?xx?is executed to transfer data between the main register and the auxiliary register, is allocated to the ?st bit of memory address ff8fh.
10 toshiba corporation tmp90c400/401 3.1.3 wait control for tmp90c400, a wait control register (waitc) is allocated to the 5th and 6th bits of memory address ff86h.
toshiba corporation 11 tmp90c400/401 3.2 memory map the tmp90c400 supports a program memory and a data memory of up to 60k bytes. the program and data memory may be assigned to the address space from 0000h to ffffh. (1) internal rom the tmp90c400 internally contains an 4k-byte rom. the address space from 0000h ~ 0fffh is provided to the rom. the cpu starts executing a program from 0000h by resetting. the addresses 0010h ~ 005fh in this internal rom area are used for the entry area for the interrupt processing. the tmp90c401 does not have a built-in rom; therefore, the address space 0000h ~ 0fffh is used as external memory space. (2) internal ram the tmp90c400 also contains a 128-byte ram, which is allocated to the address space from ff00h ~ ff7fh. the cpu allows the access to a certain ram area (ff00h ~ ff7fh, 128 bytes) by a short operation code (opcode) in a ?irect addressing mode? the addresses from ff20h to ff5fh in this ram area can be used as parameter area for micro dma processing (and for any other purposes when the micro dma function is not used). (3) internal i/o the tmp90c400 provides a 32-byte address space as an internal i/o area, whose addresses range from ff80h to ff9fh. this i/o area can be accessed by the cpu using a short opcode in the ?irect address ing mode? figure 3.2 is a memory map indicating the areas accessible by the cpu in the respective addressing mode.
12 toshiba corporation tmp90c400/401 figure 3.2 (a). memory map of tmp90c400
toshiba corporation 13 tmp90c400/401 figure 3.2 (b). memory map of tmp90c401
14 toshiba corporation tmp90c400/401 3.3 interrupt functions the tmp90c400 supports a general purpose interrupt processing mode for internal and external interrupt requests and a micro dma processing mode that enables automatic data transfer by the cpu. after the reset state is released, all interrupt requests are processed in the general purpose interrupt processing mode. however, they can be processed in the micro dma processing mode by using a dma enable register to be described later. figure 3.3 (1) is a ?wchart of the interrupt response sequence. figure 3.3 (1). interrupt response flowchart when an interrupt is requested, the request is to the i nter- rupt transmitted to the cpu via an internal interrupt contr oller. the cpu starts the interrupt processing if it is a non- maskable or maskable interrupt requested in the ei state (interrupt enable ?g (iff = ??. however, a maskable interrupt requested in the di state (iff = 0? is ignored. an interrupt request is sampled by the cpu at the falling edge of the clk signal in the last bus cycle of each instruction. by receiving an interrupt, the cpu reads out the interrupt vector from the internal interrupt controller to ?d out the interrupt source. then, the cpu checks if the interrupt requests the general purpose interrupt processing or the micro dma processing, and proceeds to each processing. as the reading of an interrupt vectors is performed in the internal operating cycles, the bus cycle results in dummy cycles. 3.3.1 general-purpose interrupt processing a general-purpose interrupt is processed as shown in figure 3.3 (2). the cpu stores the contents of the program counter pc and the register pair af (including the interrupt enable ?g (iff) before an interrupt) into the stack, and resets the interrupt enable ?g iff to ??(disable interrupts). in then transfers the value of the interrupt vector ??to the program counter, and the processing jumps to an interrupt processing program. the overhead for the entire process from accepting an interrupt to jumping to an interrupt processing program is 20 states.
toshiba corporation 15 tmp90c400/401 figure 3.3 (2). general-purpose interrupt processing flowchart an interrupt (maskable and non-maskable) processing program ends with a reti instruction. when this instruction is executed, the data previously stacked from the program counter pc and the register pair af are restored. (returns to the interrupt enable ?g (iff) before the interrupt.) after the cpu reads out the interrupt vector, the interrupt source acknowledges that the cpu accepts the request, and clears the request. a non-maskable interrupt cannot be disabled by pro- gram. a maskable interrupt, on the other hand, can be enabled or disabled by programming. an interrupt enable ?p- ?p (iff) is provided on the bit 5 of register f in the cpu. the interrupt is enabled or disabled by setting iff to ??by the ei instruction or to ??by the di instruction, respectively. if is reset to ??by the r eset operation or the acceptance of any interrupt (including non-maskable interrupt). the interrupt can be enabled after the subsequent instruction of ei instruction is exe- cuted. table 3.3 (1) lists the possible interrupt sources.
16 toshiba corporation tmp90c400/401 table 3.3 (1) interrupt sources priority order type interrupt source vector value ? 8 vector value start address of general- purpose interrupt processing start address of micro dma processing parameter 1 2 non- maskable swi instruction nmi (input from nmi pin) 02h 03h 10h 18h 0010h 0018h 3 4 5 6 7 8 9 10 maskable into (external input 0) intto (timer 0) intt1 (timer 1) intt2 (timer 2) intt3 (timer 3) int1 (external input 1) intrx (end of serial receiving) inttx (end of serial transmission) 04h 05h 06h 07h 08h 09h 0ah 0bh 20h 28h 30h 38h 40h 48h 50h 58h 0020h 0028h 0030h 0038h 0040h 0048h 0050h 0058h ff20h ff28h ff30h ff38h ff40h ff48h ff50h ff58h the ?riority order?of table 3.3 (1) shows the order of the interrupt source to be acknowledge by the cpu when more than one interrupt are requested simultaneously. in interrupt of 4 and 5 or ders are requested simultaneously, for example, an interrupt of the ?th?priority is acknowledged after a ?th?priority interrupt processing has been completed by a reti instruction. however, a lower priority interrupt can be acknowledged immediately by executing an ei instruction in a program that processes a higher priority interrupt. the internal interrupt controller merely determines the priority of the sources of interrupts to be acknowledged by the cpu when more than one interrupt are requested at a time. it is, therefore, unable to compare the priority of interrupt being executed with the one being requested. to permit another interrupt during a cetain iterrupt operation, set the interrupt enabling ?g for the source of the interrupt to be allowed, and execute the ei command. 3.3.2 micro dma processing figure 3.3 (3) is a ?w chart of the micro dma processing. parameters (addresses of source and destination, and transfer mode) for the data transfer between memories are loaded by the cpu from an address modi?d by an interrupt vector value. after the data transfer between memories according to these parameter, these parameters are updated and saved into the original locations. the cpu then decrements the number of transfers, and completes the micro dma processing unless the result is ?? if the number of transfer becomes ?? the cpu proceeds to the general-purpose interrupt processing described in the previous item.
toshiba corporation 17 tmp90c400/401 figure 3.3 (3). micro dma processing flowchart the micro dma processing is performed by using only hardware to process interrupts mostly completed by simple data transfer. the use of hardware allows the micro dma processing to handle the interrupt in a higher speed than the conventional methods using software. the cpu registers are not affected by the micro dma processing. figure 3.3 (4) shows the functions of parameters used in the micro dma processing.
18 toshiba corporation tmp90c400/401 figure 3.3 (4). parameters for micro dma processing the parameters for the micro dma processing are located in the internal ram area (see table 3.3 (1) interrupt sources). the start address of each parameter is ?f00h + interrupt vector value? from which a six bytes?space is used for the parameter. this space can be used for any other memory purposes if the micro dma processing is not used. the parameters normally consist of the number of trans- fer, addresses of destination and source, and transfer mode. the number of transfer indicates the number of data transfer accepted in the micro dma processing. the amount of data transferred by a single micro dma processing is 1 or 2 bytes. the number of transfers is 256 when the number of transfers value is ?0h? both the destination and source addresses are speci?d by 2 byte data. the address space available for the micro dma processing ranges from 0000h to ffffh. bits 0 and 1 of the transfer mode indicates the mode updating the source and/or destination, and the bit 2 indicates the data length (1 byte or 2 bytes). table 3.3 (2) shows the relation between the transfer mode and the result of updating the destination/source addresses.
toshiba corporation 19 tmp90c400/401 table 3.3 (2) addresses updated by micro dma processing transfer mode function destination address source address 000 001 010 011 100 101 110 111 1-byte transfer: fix the current source/destination addresses 1-byte transfer: increment the destination address 1-byte transfer: increment the source address 1-byte transfer: decrement the source address 2-byte transfer: fix the current source/destination addresses 2-byte transfer: increment the destination address 2-byte transfer: increment the source address 2-byte transfer: decrement the source address 0 +1 0 0 0 +2 0 0 0 0 +1 -1 0 0 +2 -2 in the 2 byte transfer mode, data are transferred as follows: (destination address) ? (source address) (destination address + 1) ? (source address + 1) similar data transfers are made in the modes that ?ecrement the source address? but the updated address are different as shown in the table 3.3 (2). address increment/decrement modes are applied to memory address space and ?ed addressing modes are applied to the i/o address space. beacause of that, the micro dma was designed for both i/o to memory transfers and memory to i/o transfers. figure 3.3 (5) shows an example of the micro dma processing that handles data receiving of internal serial i/o. this is an example of executing ?n interrupt processing program after serial data receiving?after receiving 7-frame data (assuming 1 frame = 1 byte for this example) and saving them into the memory addresses from ff00h to ff06h. call si0init ; initial setting for serial addressing. set 1, (0ffe9h) ; enable an interrupt for serial data receiving. set 1, (0ffe9h) ; set the micro dma processing mode for the interrupt. ld (0ff5oh),7 ; set the number of transfer = 7 ldw (0ff51h), 0ff00h ; set ff00h for the destination address. ldw (0ff53h), 0ffebh ; set ffebh for the source (serial receiving buffer) address. ld (0ff55h),1 ; set the transfer mode (1 byte transfer: increment destination address.) ei : : org 0050h interrupt processing program after serial data receiving reti figure 3.3 (5). example of micro dma processing
20 toshiba corporation tmp90c400/401 the bus operation in the general- purpose interrupt process- ing and the micro dma processing is shown in ?able 1.4 (2) bus operation for executing instructions?in the previous sec- tion. the micro dma processing time (when the number of trans- fer is not decremented to 0) is 46 states without regard to the 1-byte/2-byte transfer mode. figure 3.3 (6) shows the interrupt processing ?wchart. figure 3.3 (6). interrupt processing flowchart
toshiba corporation 21 tmp90c400/401 3.3.3 interrupt controller figure 3.3 (8) outlines the interrupt circuit. the left half of this ?ure represents an interrupt controller, and the right side comprises the cpu interrupt request signal circuit and halt release signal circuit. the interrupt controller consists of interrupt request flip- ?ps, interrupt enable ?gs, and micro dma enable ?gs allocated to each of 14 channels. the interrupt request flip- ?ps serve to latch interrupt requests from peripherals. each ?p-?p is reset to ??when a reset or interrupt is acknowledged by the cpu and the vector of the interrupt channel is read into the cpu, or when the cpu executes an instruction that clears an interrupt request flip-?p for the speci?d channel (write ?ector divided by 8?in the memory address ffc3h). for example, by executing. ld (ff9eh), 58h/8, the interrupt request flip-?ps for the interrupt channel ?ntt1?whose vector is 30h is reset to?? the status of an interrupt request flip-?ps is found out by reading the memory address ffc2h or ffc3h. ??denotes there is not interrupt request, and ??denotes that an interrupt is request. figure 3.3 (7) illustrates the bit con?uration indicating the status of interrupt request flip-?ps. figure 3.3 (7). con?uration of interrupt request flip-flops
22 toshiba corporation tmp90c400/401 figure 3.3 (8). block diagram of interrupt controller the interrupt enable ?gs provided for all interrupt request channels are assigned to the memory address ff9ch. setting the ?gs to ??enables an interrupt of the respective channel. these ?gs are initialized to ??by resetting. clear the interrupt enable ?g in the di status. the micro dma enable ?g also provided for each interrupt request channel is assigned to the memory address ff9dh. the interrupt processing for each channel is placed in the micro dma processing mode by setting this ?g to ?? this ?g is initialized to ??(general-purpose interrupt processing mode) by resetting. figure 3.3 (9) shows the bit con?uration of the interrupt enable ?gs and micro dma enable ?gs.
toshiba corporation 23 tmp90c400/401 interrupt common terminal mode how to set nmi p24 falling edge p2fr = 1 int0 p30 level intmr = 0 rising edge intmr = 1 int1 p31 rising edge
24 toshiba corporation tmp90c400/401 figure 3.3 (9). interrupt/micro dma enable flags
toshiba corporation 25 tmp90c400/401 3.4 standby function when a halt instruction is executed, the tmp90c400 selects one of the following modes as determined by the halt mode setting register: (1) run: suspends only the cpu operation. the power consumption remains unchanged. (2) idle1: suspends all internal circuits except the inter nal oscillator. in this mode, the power consumption is less than 1/10 of that in the normal operation. (3) idle2: operate only the internal oscillator and speci? internal i/o devices. the power consumption is about 1/3 of that in the nor mal operation. (4) stop: suspends all internal circuits including the internal oscillator. in this mode, the power consumption is considerably reduced. the halt mode set register (stbmod is assigned to the bits 2 and 3 of the memory address ffd8h in the internal i/o register area (other bits are used to control other functions). the register is reset to ?0?(run mode) by resetting. these halt state can be released by an interrupt request or reset. the methods for releasing the halt status are shown in table 3.4 (2). either a non-maskable or maskable interrupt with ei (enable interrupt) condition is acknowledged and interrupt processing is processed. a maskable interrupt with di instruction that follows the halt instruction, but the interrupt request ?g is held at ?? when the halt status is released by reset, however, note that it is not possible to hold the status (including built-in ram) in effect immediately before entering the stop status. in this case, it is recommended that an interrupt request be used for releasing. figure 3.4 (1). halt mode set register
26 toshiba corporation tmp90c400/401 3.4.1 run mode figure 3.4 (2) shows the timing for releasing the halt state by interrupts in the run/idle 2 mode. in the run mode, the system clock in the mcu continues to operate even after a halt instruction is executed. only the cpu stops executing the instruction. until the halt state is released, the cpu repeats dummy cycles. in the halt state, an interrupt request is sampled with the rising edge of the clk signal figure 3.4 (2). timing chart for releasing the halt state by interrupts in run/idle 2 modes
toshiba corporation 27 tmp90c400/401 3.4.2 idle 1 mode figure 3.4 (3) illustrates the timing for releasing the halt state by interrupts in the idle 1 mode. in the idle 1 mode, only the internal oscillator and the watchdog timer operate. the system clock in the mcu stops, and the clk signal is ?ed at the ?? in the halt state, an interrupt request is sampled asynchronously with the system clock, however the halt release (restart of operating) synchronously with the system clock. note: interrupt requests except external non-maskable interrupt (nmi ) are prohibited through the halt period in this mode. figure 3.4 (3). timing chart of halt released by interrupts in idle1 mode
28 toshiba corporation tmp90c400/401 3.4.3 idle 2 mode figure 3.4 (2) shows the timing of halt release caused by interrupts in the run/idle 2 mode. in the idle 2 mode, the halt state is released by an interrupt with the same timing as in the run mode, except the internal operation of the mcu. in the run mode, only the cpu stops executing the current instruction, and the system clock is supplied to all internal devices. in the idle 2 mode, however, the system clock is supplied to only speci? internal i/o devices. as a result, the halt state in the idle 2 mode requires only a 1/3 of the power consumed in the run mode. in the idle 2 mode, the system clock is supplied to the following i/o devices: 8-bit timer serial interface note: interrupt requests by external interrupts (int0, int1) are prohibited through the halt period in this mode. 3.4.4 stop mode the stop mode is selected to stop all internal circuits including the internal oscillator. in this mode, all pins except special pins are put in the high-impedance state, independent of the internal operation of the mcu. all interrupt request are prohibited through the halt period in this mode. (note: that the external non-maskable interrupt pin (nmi ) should be kept as ??) by resetting, this mode can be cleared. however programmable pull-up resistor port remains as pulled up. table 3.4 (1) summarizes the state of these pins in the stop mode. note, however, that the pre-halt state (the status prior to execution of halt instruction) of all output pins can be retained by setting the internal i/o register stbmod toshiba corporation 29 tmp90c400/401 *: intermediate bias is still applied to this pin in the zero cross detect mode. ? indicates that input mode/input pin cannot be used for input and that the output mode/output pin have been set to high impedance. in: the input enable status. in: the input gate is operating. fix the input voltage at either ??or ??to prevent the pin ?ating. out: the output status. note: it is necessary to leave int0 at ??until the second bus cycle of the interrupt response sequence is completed, when the stop mode is released by the level mode of int0. table 3.4 (1) state of pins in stop mode in/out drve = 0 drve = 1 p0 input mode output mode in out p1 input mode output mode in out p20 ~ p25 input mode output mode in out p26 p27 output pin output pin in out p30 ~ p33 input mode output mode in* out p34 ~ p37 input mode output mode in out p4 input mode output mode in out p5 input mode output mode in out p6 input mode output mode in in* ale clk reset x1 x2 input pin output pin input pin input pin output pin ? in ? ? ? in ?
30 toshiba corporation tmp90c400/401 o: can be used to release the halt command. ? cannot be used to release the halt command. table 3.4 (2) i/o operation during halt and how to release the halt command halt mode run idle2 idle1 stop stbmod 00 11 10 01 operation block cpu halt i/o port keeps the state when the halt command was executed. see table 3.4 (1) 8-bit timer operation halt serial interface interrupt controller nmi ooo halt releasing source interrupt int0 o intt0 oo intt1 oo intt2 oo intt3 oo int1 o intrx oo inttx oo reset oooo
toshiba corporation 31 tmp90c400/401 3.5 function of ports the tmp90c400 contains a total of 56 pins (tmp90c401: 38-pins) input/output ports. these ports function not only for the general-purpose i/o but also for the input/output of the internal cpu and i/o. table 3.5 describes the functions of these ports. table 3.5 functions of ports port name pin name no. of pins direction direction set unit resetting value pin name for internal function port 0 p00 ~ p07 8 i/o byte input ad0 ~ ad7 port 1 p10 ~ p17 8 i/o byte input a8 ~ a15 port 2 p20 ~ p23 p24 p25 p26 p27 4 1 1 1 1 i/o i/o i/o output output bit bit bit input input input output output nmi }with programmable wait }pull-up resistor rd wr port 3 p30 p31 p32 p33 p34 p35 p36 p37 1 1 1 1 1 1 1 1 i/o i/o i/o i/o i/o i/o i/o i/o bit bit bit bit bit bit bit bit input input input input input input input input int0 int1 t10 t12 }with programable to1 }pull-up resistor rxd sclk txd port 4 p40 ~ p47 8 i/o bit input port 5 p50 ~ p57 8 i/o bit input with programmable pull-up resistor port 6 p60 ~ p67 8 i/o bit input these port pins function as the general-purpose input/ output ports by resetting. the port pins, for which input or out- put is programmably selectable, function as input ports by reset- ting. a separate program is required to use them for an internal function. the tmp90c401 functions in the same way as the tmp90c400 except: port 0 always functions as address/data bus (ad0 to ad7). port 1 always functions as address bus (a8 to a15). p26 and p27 of port 2 always function as rd and wr pins, respectively.
32 toshiba corporation tmp90c400/401 3.5.1 port 0 (p00 ~ p07) port 0 os an 8-bit general-purpose i/o port p0 whose i/o function is speci?d by the control register p0cr in bit. all bits of the control register are initialized to ??by resetting, whereby port 0 turns to the input mode, and the contents of the output latch register are unde?ed. in addition to the general-purpose i/o port function, it functions as an address/data bus (ad0 ~ ad7). when access- ing an external memory, it automatically functions as an address/data bus and cleares p0cr to ?? figure 3.5 (1). port 0
toshiba corporation 33 tmp90c400/401 3.5.2 port 1 (p10 ~ p17) port 1 is an 8-bit general-purpose i/o port p1 whose i/o function is speci?d by the control register p1cr in bit. all bits of the output latch and the control register are initialized to ??by resetting, whereby port 1 is put in the input mode. in addition to the general-purpose i/o port function, it functions as a data bus (a8 ~ a15). the address bus fucntion can be speci?d by setting the external externsion control regis- ter p2fr to ?? and also setting the port 1 control regis- ter p1cr to the output mode. when the value of the port 1 control is set to ?? port 1 turns to the input mode regardless of the value of the exernal extension control register. the register is reset to ??whereby port 1 turns to the general-pur- pose i/o mode. figure 3.5 (2). port 1
34 toshiba corporation tmp90c400/401
toshiba corporation 35 tmp90c400/401 3.5.3 port 2 (p20 ~ p27) port 2 includes a 6-bit (p20 ~ p25) general-purpose i/o port and a 2-bit (p26, p27) output port (p2: memory address ff84h). i/o functions are speci?d by the control register (p2cr: mem- ory address ff85h) in bit basis. a 6-bit i/o port has a programmable pull-up register which functions when the output latch register is set to ?? in addition to i/o function p24 controls non-maskable interrupt input pin (nmi ), and p25 to p27 control external memory control. these additional functions are speci?d by the function register (p2fr: memory address ff86h). by resetting, all bits are initialized to ?? and the control/function register to ?? as a result, i/o port turns to the pull-up input port and the output port outputs ?? p26 and p27 automatically function as memory control pins (rd , wr ) when accessing an external memory, and as general-purpose ports when accessing an internal memory. for accessing an external memory, the output latch registers p26 (rd ) and p27 (wr ) should be kept at ??which is the ini- tial value after resetting. figure 3.5 (5). port 2 (except p24)
36 toshiba corporation tmp90c400/401 (1) p24/nmi p24 is a general-purpose i/o port, shared with a non- maskable interrupt input pin (nmi ). the nmi pin is selected by the function register p2fr . by set- ting nmic = 1, it turns to the nmi input pin. this bit gives the priority over the control register (p2cr). since the nmi pin is speci?d only one, the nmi pin can- not be switched to the general-purpose port. the nmic should be initialized to ??by resetting in order to switch to the general-purpose i/o port mode. figure 3.5 (6). port 24
toshiba corporation 37 tmp90c400/401 figure 3.5 (7). register for port 2
38 toshiba corporation tmp90c400/401 3.5.4 port 3 (p30 ~ p37) port 3 is an 8-bit general-purpose i/o port (p3: memory address ff87h). the i/o is selected by the control register (p3cr: memory address ff88h) in bit basis. port 3 also has a programmable pull-up resistor which functions when the output latch register is ?? by resetting, all bits are initialized to ?? and the control register to ?? as a result, port 3 turns to the pull-up input port. in addition to the i/o port function, port 3 has the external interrupt request input, timer/event counter clock input, and timer output internal serial interface functions. (1) p30 ~ p33 p30 ~ p33 are general-purpose i/o ports, shared between external interrupt request input pins (int0, int1) and timer/event counter clock input pins (ti0, ti2 ). these ports have zero-cross detection circuits, which are connected to an external capacitor. this zero-cross detection disable/enable is speci?d by the function register (p3fr: memory address ff98h). when this register is initialized to ?? by resetting, the zero-cross detection becomes disabled. figure 3.5 (8). ports 30 ~ p33
toshiba corporation 39 tmp90c400/401 (2) p34 ~ p37 p34 ~ p37 are general-purpose i/o ports, shared between the timer output pin (to1) and internal serial interface i/o pins (rxd, sclk, txd). these ports are speci?d by the control register (p3fr: memory address ff88h) and the function register (p3fr: memory address ff98h) . for example, the following is the procedures to assign p34 as to1 pin: 1) set the control register (34c: bit 4 of memory address ff88h) to ??to make the output mode, and 2) set the function register (to1: bit 4 memory address ff98h) to ?? the control an function registers are initialized to ??by resetting, and the ports turn to the general-purpose i/o port mode. note: when assigning p34, p36, and p37 as to1, sclk, and txd respectively, the pull-up register is executed not only by the value of the output latch register, but by that of to1, sclk, and txd. figure 3.5 (9). ports p34 ~ p37
40 toshiba corporation tmp90c400/401 figure 3.5 (10) register for port 3
toshiba corporation 41 tmp90c400/401 3.5.5 port 4 (40 ~ p47) port 4 is an 8-bit general-purpose i/o port (p4: memory address ff89h). it is speci?d by the control register (p4cr: memory address ff8ah) in bit basis. all bits of the output latch are initialized to ??by resetting, and port 4 turns to the input mode. figure 3.5 (11). port 4
42 toshiba corporation tmp90c400/401 figure 3.5 (12). register for port 4
toshiba corporation 43 tmp90c400/401 3.5.6 port 5 (p50 ~ p57) port 5 is an 8-bit general-purpose i/o port (p5: memory address ff8bh). it is speci?d by the control register (p5cr: memory address ff8ch) in bit basis. all bits of port 5 have the programmable pull-up register which functions when the output latch register is set to ?? all bits of the output latch are initialized to ??and the control register to ??by resetting, and port 5 turns to the pull-up input port. figure 3.5 (13) port 5
44 toshiba corporation tmp90c400/401 figure 3.5 (14). register for port 5
toshiba corporation 45 tmp90c400/401 3.5.7 port 6 (p60 ~ p67) port 6 is an 8-bit general-purpose i/o port (p6: memory address ff8dh) whose function is speci?d by the control register (p6cr: memory address ff8eh) for each bit. all bits of the output latch and the control register are initialized to ?? by resetting, and all bits of port 6 enter in the input mode. figure 3.5 (15). port p6
46 toshiba corporation tmp90c400/401 figure 3.5 (16). register for port 6
toshiba corporation 47 tmp90c400/401 3.6 timers the tmp90c400 incorporates four 8-bit timers. the four 8-bit timers can operate independently, and also function as two 16-bit timers through cascade connection. timer 2 is provided with 8-bit timer/event counter and can be used as 16-bit counter by connecting with 8-bit counter or timer 3. 8-bit interval timer mode (4 timers) 16-bit interval timer mode (2 timers) - possible arrangements: 8-bit x 2 and 16-bit x 1 8-bit programmable square wave (pulse) generation (ppg: variable duty with variable cycle) mode (timers 1, 0) 8-bit pulse width modulation (pwm: variable duty with con- stant c ycle) mode (timer 1) 8-bit event counter mode (timer 2) 16-bit event counter mode (timer 2, 3) software counter latch function (timer 2, 3) 3.6.1 8-bit timers the tmp90c400 incorporates four 8-bit interval timers (tim- ers 0, 1, 2 and 3), each of which can be operated indepen- dently. the cascade connection of timer 0 and 1, or timer 2 and 3 allows these timers used as 16-bit internal timers. figure 3.6 (1) shows a block diagram of the 8-bit timers (timer 0 and timer 1). figure 3.6 (2) shows a block diagram of the 8-bit timer/ event counters (timer 2 and timer 3). each interval timer is composed of an 8-bit up-counter, an 8-bit timer register, with a timer tlip-?p (tff1) provided to each pair of timer 0/1. internal clocks (?1, ?16 and ?256) for the input clock sources to the interval timers are generated by the 9-bit prescaler shown in figure 3.6 (3). their operating modes of the 8-bit timers and ?p-?ps are controlled by 4 control registers (tclk, tffcr, tmod and trun).
48 toshiba corporation tmp90c400/401 figure 3.6 (1). block diagram of 8-bit timers (timers 0 and 1)
toshiba corporation 49 tmp90c400/401 figure 3.6 (2). block diagram of 8-bit timer/counter (timers 2 and timer 3)
50 toshiba corporation tmp90c400/401 prescaler a 9-bit prescaler is provided to further divide the clock frequency already divided to a 1/4 of the frequency of the source clock (fc). it generates a input clock pulse for the 8-bit timers, 16-bit timer/event counter, the baud-rate generator, etc. for the 8-bit timers, three types of clock are generated (?1, ?16 and ?256) are used. the prescaler can be run or stopped by using the 5th bit trun of the timer control register trun. setting to ??makes the prescaler count, and setting it to ??clears the prescaler to stop. is initialized to ??by resetting, and clears and stop the prescaler . figure 3.6 (3). prescaler
toshiba corporation 51 tmp90c400/401 up-counter this is an 8-bit binary counter that counts up by an input clock pulse speci?d by an 8-bit timer clock control register (tclk) and an 8-bit timer mode register. the input clock pulse for timer 0 and 2 is selected from ?1 (8/fc), ?16 (128/fc) and ?256 (2048/fc) according to the setting of the tclk register. example: when setting tclk = 0,1 ?1 is selected as the input clock pulse for timer 0. the input clock pulse to timers 1 and 3 is selected accord- ing to the operating mode. in the 16-bit timer mode, the over?w output of timers 0 and 2 is automatically selected as the input clock pulse, regardless of the setting of the tclk register. in the other operating modes, the clock pulse is selected among the internal clocks ?1, ?16 and ?256, and the output of the timers 0 and 2 comparator (match signal) by the tclk register setting. example: if tmod = 0,1, the over?w output of timer 0 is selected as the input clock to timer 1. (16-bit timer mode) if tmod = 0,0 and tclk = 0,1, ?1 is selected as the input clock to timer 1. (8-bit timer mode) the operating mode is selected by the tmod register. this register is initialized to tmod = 0,0/tmod = 0,0 by resetting, whereby the up-counter is place in the 8-bit timer mode. functions, count, stop or clear of the up-counter can be controlled for each interval timer by the timer control register trun. by resetting, all up-counters are cleared to stop the timers.
52 toshiba corporation tmp90c400/401 figure 3.5 (4). 8-bit timer mode register tmod
toshiba corporation 53 tmp90c400/401 figure 3.6 (5). 8-bit timer clock control register (tclk)
54 toshiba corporation tmp90c400/401 figure 3.6 (6). timer/serial channel control registers (trun)
toshiba corporation 55 tmp90c400/401 figure 3.6 (7). 8-bit timer flip-flop control register (tffcr)
56 toshiba corporation tmp90c400/401 a timer registers 8-bit registers are provided to set the interval time. when the set value of a timer register matches that of an up-counter, the match signal of their comparators turn to the active mode. if ?0h?is set, this signal becomes active when the up-counter over?ws. when a new value is written to this register, it is then immediately input to the comparator. the value of the timer register 0 and timer register 1 cannot be read out. timer registers 2 and 3 are allocated to the same address with counter latch registers. the readout value becomes the counter latch register value. the written value becomes the timer register value. ? comparators a comparator compares the values in an up-counter and a timer register. when they matches, the up-counter is cleared to ?? and an interrupt signal (intt0 ~ 3) is generated. if the timer ?p-?p inversion is enabled by the timer ?p-?p control register, the timer ?p-?p is inverted. ? timer flip-?p (timer f/f) the timer ?p-?p is inverted by the match signal (output by comparator). its status can be output to the timer output pin to1 (also used as p34). this timer f/f is controlled by a timer ?p-?p control register (tffcr). in the case of tff1 (timer f/f for timer 0 and timer 1), the ?p-?p operation is described as follows (refer to figure 3.6 (7)): ?tffcr is a timer selection bit for inversion of tff1. in the 8-bit timer mode, inversion is enabled by the match signal from timer 0 if this bit is set to ?? or by the signal from timer 1 is set to ?? in any other mode, must be always set to ?? it is initialized to ??by resetting. tffcr controls the inversion of tff1. setting this bit to ??enables the inversion and setting it to ?? disables. ff1ie is initialized to ??by resetting. ?the bits tffcr are used to set/reset tff1 or enable its inversion by software. tff1 is reset by writing ?, 0? set by ?, 1?and inverted by ?, 0? the 8-bit timers operate as follows: (1) 8-bit timer mode the four interval timers 0, 1, 2 and 3 can operate independently as an 8-bit interval timer. timer 2 and 3 do not provide timer output operation, but timer operations are the same as for timer 0 and 1. the operation of timer 1 is described in the following. generating interrupts at specified intervals periodic interrupts can be generated by using timer 1 (intt1) in the following procedure: 1) stop timer 1, 2) set the desired operating mode, input clock and cycle time in, the registers tmod, tclk and treg1, 3) set intt1 to ?nable? and 4) start the counting of timer 1. example: to generate timer 1 interrupt every 4.0 m s at fc =10mhz, the registers should be set as follows:
toshiba corporation 57 tmp90c400/401 refer to table 3.6 (1) for selecting the input clock: table 3.6 (1) 8-bit timer interrupt cycle and input clock interrupt cycle @fc = 10mhz resolution input clock 0.8 m s ~ 204.8 m s 12.8 m s ~ 3.2768ms 204.8 m s ~ 52.4288ms 0.8 m s 12.8 m s 204.8 m s ?1 (8/fc) ?16 (128/fc) ?256 (2048/fc) generating pulse at 50% duty the timer ?p-?p is inverted at speci?d intervals, and its status is output to a timer output pin to1 (only tim- ers 0 and 1). example: to output pulse from to1 at fc = 10mhz every 4.8 m s, the registers should be set as follows: this example uses timer 1, but the same operation can be effected by using timer 0.
58 toshiba corporation tmp90c400/401 figure 3.6 (8). pulse output (50% duty) timing chart a making timer 1 counting up timer 0 match signal. select the 8-bit timer mode, and set the comparator output of timer 0 as the input clock to timer 1. figure 3.6 (9)
toshiba corporation 59 tmp90c400/401 ? output inversion by software the timer ?p-?ps can be inverted by software regardless of the timer operation. writing ?0?into tffcr inverts tff1 . ? initial setting of timer flip-flops the timer ?p-?ps can be initialized to either ??or ?? without regard to the timer operation. tff1 is initialized to ??by writing ?0? and to ?? by writing ?1?into tffcr . note: data from the timer ?p-?ps and timer registers cannot be read. (2) 16-bit timer mode a pair of timer 0 and timer 1 or timer 2 and timer 3 can be used as one 16-bit interval timer. timers 2 and 3 do not provide output function, but timer operations are the same with timer 0 and 1. the operation of a timer pair timer 0 and timer 1 is discussed. cascade connection of timer 0 and timer 1 to use them as a 16-bit interval timer requires to set the of the mode register tmod to ?,1? by selecting the 16-bit timer mode, the over?w output of timer 0 is automatically selected as the input clock to timer 1, regardless of the set value of the clock control register tclk. the input clock to timer 0 is selected by tclk. table 3.6 (2) shows the relationship between timer (interrupt) cycle and input clock selection. table 3.6 (2) 16-bit timer (interrupt) cycle and input clock timer (interrupt) cycle @fc = 10mhz resolution input clock to timer 0 0.8 m s ~ 52.43ms 0.8 m s ?1 (8/fc) 12.8 m s ~ 838.86ms 12.8 m s ?16 (128/fc) 204.8 m s ~ 13.425s 204.8 m s ?256 (256/fc) the lower 8 bits of the timer (interrupt) cycle is set by treg0 and the upper eight bits of that is set by treg1. note that treg0 must be always set ?st (writing data into treg0 disables the comparator temporarily, which is restarted by writing data into treg1). example: to generate interrupts intt1 at fc = 8mhz every 1 second, the timer registers treg0 and treg1 should be set as follows: as ?16 (= 16 m s @ 8mhz) is selected as the input clock, 1 sec/16 m s = 62500 = f424h therefore, treg1 = f4h treg0 = 24h the match signal is generated by timer 0 comparator each time the up-counter uc0 matches treg0. in this case, the up-counter uco is not cleared, but the interrupt intt0 is generated. timer 1 comparator also generates the match signal each timer the up-counter uc1 match treg1. when the match signal is generated simultaneously from comparators of timer 0 and timer 1, the up-counters uc0 and uc1 are cleared to ?? and the interrupt intt1 is generated. if the timer ?p-?p inversion is enabled by the timer flip-?p control register, the timer ?p-?p tff1 is inverted at the same time.
60 toshiba corporation tmp90c400/401 example: given treg1 = 04h and treg0 = 80h, figure 3.6 (10) timer 0 timer 1 intt0 to1 match intt1 to1 match 16-bit timer mode (count-up timer 1 by overflow of timer 0) interrupt is generated can't output (can? output the matching with treg0) treg0 (continue counting when match) interrupt is generated can output *can output the matching with both treg0 and treg1) treg1 * 2 8 + treg0 (16-bit) (cleared by matching with both registers.) 8-bit timer mode (count-up timer 1 by matching of timer 0) interrupt is generated can output (timer 0 or timer 1) treg0 (clear when match) interrupt is generated can output (timer 0 or timer 1) treg1*treg0 (multiplied valve) (cleared by matching) (3) 8-bit ppg (programmable pulse generation) output mode pulse can be generated at any frequency and duty rate by timer 1 or timer 3. the output pulse may be either low-or high-active. in this mode, timers 0 cannot be used. pulse is output to to1 (shared with p37).
toshiba corporation 61 tmp90c400/401 in this mode, programmable pulse is generated by the inversion of the timer output put each time the 8-bit up- counter 1 (uc1) matches the timer register treg0 or treg1. note that the set value of treg0 must be smaller than that of treg1. in this mode, the up-counter uc0 of timer 0 cannot be used (set trun = 1, and count the timer 0). the ppg mode is shown in figure 3.6 (11). figure 3.6 (11). block diagram of 8-bit ppg mode example: generate pulse at 50khz and 1/4 duty rate (@fc = 8mhz)
62 toshiba corporation tmp90c400/401 determine the set value of the timer registers. to obtain the frequency of 50khz, pulse cycle t = 1/50khz = 20 m s when ?1 = 1 m s (@ 8mhz), 20 m s ? 1 m s = 20 consequently, the timer register 1 (treg1) should be set to 20 = 14h. given a 1/4 duty, t x 1/4 = 20 x 1/4 = 5 m s 5 m s ? 1 m s = 5 as a result, the timer register 0 (treg0) should be set to 5 = 05h. precautions for ppg output by rewriting the content of the treg (timer register), it is possible to make tmp90c400 output ppg. however, be careful, since the timing to rewrite treg differs depending on the pulse width of ppg to be set. this problem is explained below by an example. example: to output ppg through 8 bit timers 0 and 1 treg0: pulse width treg1: cycle
toshiba corporation 63 tmp90c400/401 the pulse width is normally changed by the interrupt (intt1) process routine in each cycle. however, when the pulse width to be set (the value to be written in treg0) is small, trouble may occur, in that the timer counter exceeds the value of treg0 before the interrupt process routine is set. therefore, it is recommended to make the following decisions in intt0 and intt1 interrupt processes. intt0 process routine: the value of treg0 is rewritten only when the value to be written in treg0 is smaller than the cur rent value of treg0. intt1 process routine: on the contrary to intt0, treg0 is written only when the value to be written in treg0 is larger than the current value of treg0. tmp90c400 cannot read the content of treg, so it is necessary to buffer the content of treg in a ram (or the like) for making the above judgement. (4) 8-bit pwm (pulse width modulation) mode this mode is only available for timer1, and generates 8-bit resolution pwm. pwm is output to to1 pin (shared with p34). timer 0 can be used as 8-bit timers. the inversion of the timer output occurs when the up-counter (uc1) matches the set value of the timer register treg1, as well as when an over?w of 2 n - 1 (n = 6, 7 or 8 selected by tmod ) occurred at the counter. the up-counter uc1 is cleared by the occurrence of an over?w of 2 n - 1. the following condition must be obtained when this pwm mode is used: (set value of timer register) < (set over?w value of 2 n - 1 counter) (set value of timer register) 1 0 the pwm mode is shown in figure 3.6 (12).
64 toshiba corporation tmp90c400/401 figure 3.6 (12). block diagram of 8-bit pwm mode example: generate the following pwm to the to1 pin (p34) at fc = 10mhz. assuming the pwm cycle is 50.4 m s when ?1 = 0.8 m s and @fc = 10mhz, 50.4 m s/0.8 m s = 63 = 2 6 - 1 consequently, n should be set at 6 (tmod1, 0 = 01). given the ??level period of 36 m s, setting ?1 = 0.8 m s results: 36 m s/0.8 m s = 45 = 2dh. as a result, treg1 should be set at 2dh.
toshiba corporation 65 tmp90c400/401 table 3.6 (3) pwm cycle and selection of 2 n - 1 counter expression pwm cycle (@fc = 10mhz) ?1 (8/fc) ?16 (128/fc) ?256 (2048/fc) 2 6 - 1 (2 6 - 1)x ?n 50.4 m s 806.4 m s 12.9ms 2 7 - 1 (2 7 - 1)x ?n 101.6 m s 1625.6 m s 26.0ms 2 8 - 1 (2 8 - 1)x ?n 204.0 m s 3264.0 m s 52.2ms precautions for pwm output tmp90c400 can output pwm by the 8-bit timer. however, changing the pulse width of pwm requires special care. this problem is explained by the following example. example: to output pwm by 8-bit timer treg1: pulse width cycle: fixed (2 6 - 1, 2 7 - 1, 2 8 - 1) in the pwm mode, intt1 occurs at the coincidence with treg1. however, the pulse width cannot be changed directly using the interrupt. (depending on the value of treg1 to be set, coincidence with treg1 may be detected again in a single cycle, inverting the timer output.) to eliminate this problem in changing the pulse width, it is effective the halt the timer with the intt1 process, modify the value of treg1, set the timer output to ?? and restart the timer. in the mean time, the output waveform loses shape when the pulse width is changed. this method is valid for a system that allows a deformed output waveform.
66 toshiba corporation tmp90c400/401 3.6.2 8-bit timer/event counter (1) event counter mode timer 2 is an 8-bit timer/event counter. it functions as not only as the 8-bit timer which is explained previ- ously, but also as the counter. timer 2 turns to the event counter mode by setting the input clock of timer 2 as the external counter (ti2). therefore, timer 2 can be used as an 8-bit counter, and timer 3 and an 8-bit timer. timers 2 and 3 turn to a 16-bit counter by connecting to a cascade . the counter counts up at the rising edge of the ti2 counter input . the ti2 pin is also used for p33 and has the zero-cross detection function. to t12 pin is speci?d by setting tclk to ?, 0?
toshiba corporation 67 tmp90c400/401 (2) software counter latch in an event counter mode, the up-counter value can be written to a counter latch register by the current running software. the present up-counter value is written to counter register latch treg2 or treg3 for every setting of register tffcr or containing ?? a prescaler should be set in ?un?mode by setting register + to ?? example: to latch the counter value every 40 m s at fc = 10mhz, the registers should be set as follows: the latched counter value can be read by reading timer register 2.
68 toshiba corporation tmp90c400/401 3.7 serial channel the tmp90c400 incorporates a serial i/o channel for full duplex asynchronous transmission (uart) and i/o expansion. the serial channel has the following operating modes: the mode 3 accommodates a wake-up function to start the slave controllers in a controller serial link (multi-controller system). figure 3.7 (1) shows the data format (1-frame data) in each mode. figure 3.7 (1). data formats
toshiba corporation 69 tmp90c400/401 data received and transmitted are stored temporarily into separate buffer registers to allow independent transmission and receiving (full-duplex). in the i/o interface mode, however, the data transfer is half-duplex due to the single sclk (serial clock) pin is used for transmission and receiving. serial channel pins (rxd, scl, txd pins) are shared among p35, p36 and p37, respectively. the pin function is selected by p3cr and p3fr registers. p35 can be used as rxd pin by setting p3cr to ?? also p36 and p37 can be used as sclk and txd pins by setting p3cr6 to 11 and p3fr to 11, respectively. the receiving buffer register has a double-buffer structure to prevent overruns. the one buffer receives the next frame data while the other buffer stores the received data. in the uart mode, a check function is added not to start the receiving operation by error start bits due to noise. the channel starts receiving data only when the start bit is detected to be normal at least twice in three samplings. when an request is issued to the cpu to transmit data after the transmitting buffer becomes empty, or to read data after the receiving buffer stores data, the interrupt inttx or intrx occurs respectively, in receiving data, the ?g sccr is set when an overrun error, or framing error occurs accordingly.
70 toshiba corporation tmp90c400/401 3.7.1 control registers the serial channel is controlled by ?e control registers (schmod, sccr, trun, p3cr, and p3fr). the received/ transmitted data are stored into scbuf. figure 3.7 (2). serial channel mode register
toshiba corporation 71 tmp90c400/401 figure 3.7 (3). serial channel control register figure 3.7 (4). serial transmission/receiving buffer register
72 toshiba corporation tmp90c400/401 figure 3.7 (5). timer/serial channel operation control register
toshiba corporation 73 tmp90c400/401 figure 3.7 (6). port 3 function register
74 toshiba corporation tmp90c400/401 3.7.2 architecture figure 3.7 (8) is a block diagram of the serial channel. figure 3.7 (8). block diagram of serial channel
toshiba corporation 75 tmp90c400/401 baud-rate generator the baud-rate generator comprises a circuit that generates a clock pulse to determine the transfer speed for transmission/receiving in the asynchronous communication (uart) mode. the input clock to the baud-rate generator ?4 (fc/32), ?16 (fc/128), ?64 (fc/512) or ?256 (fc/2048) is generated by the 9-bit prescaler. one of these input clocks are selected by the timer/serial channel control register trun . also, either no frequency division or 1/2 division can be selected by the serial channel mode register scmod . table 3.7 (1) shows the baud-rate when fc = 9.8304mhz. @fc = 9.8304mhz table 3.7 (1) baud rate selection (1) unit [bps] input clock no division (sc1, 0 = 01) 1/2 division (sc1, 0 = 11) 00 ?256 (fc/2048) 300 150 01 ?64 (fc/512) 1200 600 10 ?6 (fc/128) 4800 2400 11 ?4 (fc/32) 19200 9600 table 3.7 (2) baud rate selection (2) (when use timer 2 with ?1) unit [kbps] treg2/fc 12.288 mhz 12 mhz 9.8304 mhz 8 mhz 6.144 mhz 01h 96 76.8 62.5 48 02h 48 38.4 31.25 24 03h 32 31.25 16 04h 24 19.2 12 05h 19.2 - 9.6 08h 12 9.6 6 0ah 9.6 4.8 10h 6 4.8 3 14h 4.8 2.4 input clock of timer 2 ?1 = fc/8 ?16 =fc/128 ?256=fc/2048
76 toshiba corporation tmp90c400/401 serial clock generating circuit this circuit generates the basic transmit/ receive clock. 1) i/o interface mode it generates a clock at a 1/8 frequency (1.25mbit/s at 10mhz) of the system clock (fc). this clock is output from the sclk pin (also used as p36). 2) asynchronous communication (uart) mode a basic clock (sioclk) is generated based on the above baud rate generator clock, the internal clock ? (fc/2) (sioclk = 5mhz, transfer speed = 312.5kb.p.s at 10mhz). or the match signal from timer 2, as selected by scmod register. a receiving counter the receiving counter is a 4-bit binary counter used in the asynchronous communication (uart) mode and is counted by using sioclk. 16 pulse of sioclk is used for receiving 1-bit data. the data are sampled three timers a 7th, 8th and 9th pulses and evaluated by the rule of majority. for example, if data sampled at the 7th, 8th and 9th clock are ?? ??and ?? the received data is evaluated as ?? the sampled data ?? ??and ??is evaluated that the received data is ?? ? receiving control 1) i/o interface mode the rxd signal is sampled on the rising edge of the shift clock which is output to the sclk pin. 2) asynchronous communication (uart) mode the receiving control features a circuit for detecting the start bit by the rule of majority. when two or more ?? are detected during 3 samples, it is recognized as nor- mal start bit and the receiving operation starts. receiv- ing data being received are also evaluated by the majority logic while receiving data. ? receive buffer the receive buffer has a double-buffer structure to prevent overruns. receive data are stored into the receive buffer 1 (shift register type) for each 1 bit. when 7 or 8 bits data are stored in the receive buffer 1, the stored data is transferred to the receive buffer 2 (scbuf), and the interrupt intrx occurs at the same time. the cpu reads out the receive buffer 2 (scbuf). data can be stored into the receive buffer 1 before the cpu reads out the receive buffer 2 (scbuf). note, however, that an overrun occurs unless the cpu reads out the receive buffer 2 (scbuf) before the receive buffer 1 receiving all bits of the next data. when an overrun occurres, the data in the receive buffer 2 and sccr are not lost, however, that in the receive buffer 1 are lost. sccr stores the msb in the 9-bit uart mode. in the 9-bit uart mode, setting scmod to ?? enables the wake-up function of the slave controllers, and the interrupt intrx occurs only if sccr = ?? ? transmission counter this is a 4-bit binary counter used in the asynchronous communication (uart) mode. like the receiving counter, it counts based on soiclk to generate a transmission clock txdclk for every 16 counts.
toshiba corporation 77 tmp90c400/401 ? transmission control 1) i/o interface mode data in the transmission buffer are output to the txd pin bit by bit at the rising edge of the shift clock output from the sclk pin. 2) asynchronous communication (uart) mode when the cpu have written data into the transmission buffer, transmission is started with the next rising edge of txdclk, and a transmission shift clock txdsft is generated. ? transmission buffer the transmission buffer scbuf shifts out the data written by the cpu from the lsb as based on the shift clock txdsft (same period as tcdclk) generated by the transmission control unit. when all bits are shifted out, the transmission buffer becomes empty, generating the interrupt inttx. signal generation timing 1) uart mode note: the occurrence of a framing error is delayed until after interruption. therefore, to check for framing error during interrupt operation, an addition operation, such as waiting for 1-bit time, becomes necessary. 2) i/o expansion mode receiving mode 9 bit 8 bit, 7 bit interrupt timing center of last bit (bit 8) center of stop bit framing error timing center of stop bit - over-run error timing center of last bit (bit 8) - transmitting mode 9 bit 8 bit, 7 bit interrupt timing just before the stop bit ? interrupt timing of receiving just after the last sclk rising interrupt timing of transmitting -
78 toshiba corporation tmp90c400/401 3.7.3 operation (1) mode 0 (i/o interface mode) this mode is used to increase the number of i/o pins of the tmp90c400. the tmp90c400 supplies the transmit/receive data and a synchronous clock (sclk) to an external shift register. figure 3.7 (9). i/o interface mode transmission each timer the cpu writes data into the transmission buffer, 8-bit data are output from txd pin. when all data are output, irfh is set, and the interrupt inttx occurs. figure 3.7 (10). transmitting operation (i/o interface mode)
toshiba corporation 79 tmp90c400/401 example: when transmitting data from p33 pin, the control registers should be set as described below. receiving each time the cpu reads the receive data and clears the receive interrupt ?g irfh , the next data are shifted into the receive buffer 1. when 8-bit data are received, the data are transferred to the receive buffer 2 (scbuf), which sets and generates interrupt intrx. for receiving data, the receiving enable state is previously set scmod = 1. figure 3.7 (11). receiving operation (i/o interface mode)
80 toshiba corporation tmp90c400/401 example: when receiving from p35 pin, the control registers should be set as described below. (2) mode 1 (7-bit uart mode) the 7-bit uart mode is selected by setting the serial channel mode register scmod to ?1? example: when transmitting data with the following format, the control registers should be set as described below.
toshiba corporation 81 tmp90c400/401 (3) mode 2 (8-bit uart mode) the 8-bit uart mode is selected by setting scmod to ?, 0? example: when receiving data with the following format, the control registers should be set as described below. (4) mode 3 (9-bit uart mode) the 9-bit uart mode is selected by setting scmod = ?1? the msb (9th bit) is written into scmod for transmission, and into sccr for receiving. writing into or reading from the buffer must begin with the msb (9th bit) followed by scbuf. w ake-up function in the 9-bit uart mode, setting scmod to ?? allows the wake-up operation as the slave controllers. the interrupt intrx occurs only when sccr = 1.
82 toshiba corporation tmp90c400/401 note: for the wake-up operation, p33 should be always selected as the txd pin of the slave controllers, and put in the open drain output mode. figure 3.7 (12). serial link using wake-up function
toshiba corporation 83 tmp90c400/401 protocol select the 9-bit uart mode for the master and slave controllers. set the scmod bit of each slave controller to ??to enable data receiving. a the master controller transmits 1-frame data including the 8-bit select code for the slave controllers. the msb (8-bit) scmod is set to ?? ? each slave controller receives the above frame, and clears the bit to ??if the above select code matches its own select code. ? the master controller transmits data to the speci?d slave controller (whose bit is cleared to ?? while setting the msb (bit 8) to ?? ? the slave controllers (with the scmod bit remaining at ?? ignore the receive data since the msb (sccr ) are set to ??to disable the inter- rupt intrx. when the bit is cleared to ?? the interrupt intrx is generated and receive data are read. the slave controllers (wu = 0) transmits data to the master controller. it is possible that the the master controller to be indicated the end of data received by this transmit data. example: link two slave controllers serially with the master controller, and use the internal clock ? (fc/2) as the transfer clock.
84 toshiba corporation tmp90c400/401 (note) x: dont care-: no change
toshiba corporation 85 tmp90c400/401 4. electrical characteristics TMP90C400N/tmp90c400f/ tmp90c401n/tmp90c401f note: i dar is guaranteed for a total of up to 8 optional ports. 4.1 absolute maximum ratings symbol parameter rating unit v cc supply voltage -0.5 ~ + 7 v v in input voltage -0.5 ~ v cc + 0.5 v p d power dissipation (ta = 85?) f 500 mw n 600 t solder soldering temperature (10s) 260 c t stg storage temperature -65 ~ 150 c t opr operating temperature -40 ~ 85 c 4.2 dc characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter min max unit test conditions v il input low voltage (p0) -0.3 0.8 v v il1 p1, p2, p3,p4, p5, p6 -0.3 0.3v cc v v il2 reset , nmi -0.3 0.25v cc v v il3 ea -0.3 0.3 v v il4 x1 -0.3 0.2v cc v v ih input high voltage (p0) 2.2 v cc + 0.3 v v ih1 p1, p2, p3,p4, p5, p6 0.7v cc v cc + 0.3 v v ih2 reset , nmi 0.75v cc v cc + 0.3 v v ih3 ea v cc - 0.3 v cc + 0.3 v v ih4 x1 0.8v cc v cc + 0.3 v v ol output low voltage 0.45 v i ol = 1.6ma v oh v oh1 v oh2 output high voltage 2.4 0.75v cc 0.9v cc v v v i oh = -400 m a i oh = -100 m a i oh = -20 m a i dar darlington drive current (8 i/o pins) (note) -0.1 -3.5 ma v ext = 1.5v r ext = 1.1k w i li input leakage current 0.02 (typ) 5 m a 0.0 vin v cc i lo output leakage current 0.05 (typ) 10 m a 0.2 vin v cc - 0.2 i cc operating current (run) idle 1 idle 2 20 (typ) 1.5 (typ) 6 (typ) 40 5 15 ma ma ma tosc = 10mhz (25%up @12.5mhz) stop (ta = -40 ~ 85 c) stop (ta = 0 ~ 50 c) 0.05 (typ) 50 10 m a m a 0.2 vin v cc - 0.2 v stop power down voltage (@stop) 2 ram back up 6v v il2 = 0.2v cc , v ih2 = 0.8v cc r rst reset pull up register 50 150 k w cio pin capacitance 10 pf testfreq = 1mhz v th schmitt width reset , nmi 0.4 1.0 (typ) v
86 toshiba corporation tmp90c400/401 ac measuring conditions output level: high 2.2v/low 0.8v, c l = 50pf (however, cl = 100pf for ad0 ~ 7, a8 ~ 15, ale, rd , wr ) input level: high 2.4v/low 0.45v (ad0 ~ ad7) high 0.8v cc /low 0.2v cc (excluding ad0 ~ ad7) 4.3 ac characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) cl = 50pf ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t osc oscillation cycle ( = x) 80 1000 100 80 ns t cyc clk period 4x 4x 400 320 ns t wh clk high width 2x - 40 160 120 ns t wl clk low width 2x - 40 160 120 ns t al a0 ~ 7 effective address ? ale fall 0.5x - 15 35 25 ns t la ale fall ? a0 ~ 7 hold 0.5x - 15 35 25 ns t ll ale pulse width x - 40 60 40 ns t lc ale fall rd /wr fall 0.5x - 30 20 10 ns t cl rd /wr ? ale rise 0.5x - 20 30 20 ns t acl a0 ~ 7 effective address ? rd /wr fall x - 25 75 55 ns t ach upper effective address ? rd /wr fall 1.5x - 50 100 70 ns t ca rd /wr fall ? upper address hold 0.5x - 20 30 20 ns t adl a0 ~ 7 effective address ? effective data input 3.0x - 35 265 205 ns t adh upper effective address ? effective data input 3.5x - 55 295 225 ns t rd rd fall ? effective data input 2.0x - 50 150 110 ns t rr rd pulse width 2.0x - 40 160 120 ns t hr rd rise ? data hold 0 0?ns t rae rd rise ? address enable x - 15 85 65 ns t ww wr pulse width 2.0x - 40 160 120 ns t dw effective data ? wr rise 2.0x - 50 150 110 ns t wd wr rise ? effective data hold 0.5x - 10 40 30 ns t ackh upper address ? clk fall 2.5x - 50 200 150 ns t ackl lower address ? clk fall 2.0x - 50 150 110 ns t ckha clk fall ? upper address hold 1.5x - 80 70 40 ns t cck rd /wr ? clk fall x - 25 75 55 ns t ckhc clk fall ? rd /wr rise x - 60 40 20 ns t dck valid data clk fall x - 50 50 30 ns t cwa rd /wr fall ? valid wait x - 40 60 40 ns t awal lower address ? valid wait 2.0x - 70 130 90 ns t wah clk fall ? valid wait hold 0 0?ns t awah upper address ? valid wait 2.5x - 70 180 130 ns t cpw clk fall ? port data output x + 200 300 280 ns t prc port data input ? clk fall 200 200 200 ns t cpr clk fall ? port data hold 100 100 100 ns
toshiba corporation 87 tmp90c400/401 4.4 zero-cross characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter condition min max unit v zx zero-cross detection input ac coupling c = 0.1 m f 1 1.8 vac p - p a zx zero-cross accuracy 50/60hz sine wave 135 mv f zx zero-cross detection input frequency 0.04 1 khz 4.5 serial channel timing-i/o interface mode v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) cl = 50pf ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t scy serial port clock cycle time 8x 800 640 ns t oss output data setup sclk rising edge 6x - 150 450 330 ns t ohs output data hold after sclk rising edge 2x - 120 80 40 ns t hsr input data hold after sclk rising edge 0 0?ns t srd sclk rising edge to input data valid 6x-150 450 330 ns 4.6 8-bit event counter v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t vck ti2 clock cycle 8x + 100 900 740 ns t vckl ti2 low clock pulse width 4x + 40 440 360 ns t vckh ti2 high clock pulse width 4x + 40 440 360 ns 4.7 interrupt operation v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 12.5mhz) symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t intal nmi , int0 low level pulse width 4x 400 320 ns t intah nmi , int0 high level pulse width 4x 400 320 ns t intbl int1 low level pulse width 8x + 100 900 740 ns t intbh int1 high level pulse width 8x + 100 900 740 ns
88 toshiba corporation tmp90c400/401 4.8 i/o interface mode timing
toshiba corporation 89 tmp90c400/401 4.9 timing chart
90 toshiba corporation tmp90c400/401 5. table of special function registers the special function registers include the i/o ports and periph- eral control registers allocated to the 32-byte addresses from ff80h to ff9fh. (1) i/o port (2) i/o port control (3) timer/event counter control (4) serial channel control (5) inrerrupt control (6) standby mode control tmp90c400 special function register address list address symbol address symbol ff80h p0 ff90h treg0 ff81h p0cr ff91h treg1 ff82h p1 ff92h treg2 ff83h p1cr ff93h treg3 ff84h p2 ff94h tclk ff85h p2cr ff95h tffcr ff86h p2fr ff96h tmod ff87h p3 ff97h trun ff88h p3cr ff98h p3fr ff89h p4 ff99h scmod ff8ah p4cr ff9ah sccr ff8bh p5 ff9bh scbuf ff8ch p5cr ff9ch intef ff8dh p6 ff9dh dmaef ff8eh p6cr ff9eh irfr ff8fh stbmod ff9fh intmr
toshiba corporation 91 tmp90c400/401 note: read/write r/w: either read or wirite is possible r: only read is possible. w: only write is possible. (1) i/o port msb lsb symbol name address 7 6 5 4 3 2 1 0 p0 port 0 ff80h p07 p06 p05 p04 p03 p02 p01 p00 r/w input mode p1 port 1 ff82h p17 p16 p15 p14 p13 p12 p11 p10 r/w input mode p2 port 2 ff84h p27 p26 p25 p24 p23 p22 p21 p20 r/w input mode (with pull-up register ) p3 port 3 ff87h p37 p36 p35 p34 p33 p32 p31 p30 r/w iput mode (with pull-up register) p4 port 4 ff89h p47 p46 p45 p44 p43 p42 p41 p40 r/w input mode (with pull-up register) p5 port 5 ff88h p57 p56 p55 p54 p53 p52 p51 p50 r/w input mode (with pull-up register) p6 port 6 ff8dh p67 p66 p65 p64 p63 p62 p61 p60 r/w input mode (2) i/o port control msb lsb symbol name address 76543 2 1 0 p0cr port 0 control reg. ff81h (prohibit rmw) p07c p06c p05c p04c p03c p02c p01c p00c w 00000 0 0 0 0: in 1: out (i/o selected bit by bit) p1cr port 1 control reg. ff83h (prohibit rmw) p17c p16c p15c p14c p13c p12c p11c p10c w 00000 0 0 0 0: in 1: out (i/o selected bit by bit) p2cr port 2 control reg. ff85h (prohibit rmw) p25c p24c p23c p22c p21c p20c w 00000 0 0 0 0 : in 1 : out (i/o selected bit by bit)
92 toshiba corporation tmp90c400/401 note: prohibit rmw: prohibit read modify write (prohibit bit/res/set instructions) p2cr port 2 function reg. ff86h (prohibit rmw) waitc1 waitc0 nmic ext r/w r/w r/w w 00000 0 0 wait control 00 : 2state wait 01 : normal wait 10 : non wait 11 : time r 0/1 output nmi control 0 : general- purpose port 1: input nmi p3cr port 3 control reg. ff88h (prohibit rmw) p37c p36c p35c p34c p33c p32c p31c p30c w 00000 0 0 0 0 : in 1 : out (i/o selected bit by bit) p3cr port 3 function reg. ff98h ode txdc sclk toe zce3 zce2 zce1 zce0 w 00000 0 0 0 p37control 0 : cmos 1 : open drain p37 control 0 : general- purpose port 1 : txd p36 control 0 : general- purpose port 1 : sclk p34 control 0 : general purpose port 1 : to1 p33 control : p32 control p31 control p30 control 0 : general-purpose port 1 : zcd enable (input only) p4cr port 4 control reg. ff8ah (prohibit rmw) p47c p46c p45c p44c p43c p42c p41c p40c w 00000 0 0 0 0: in 1: out (i/o selected bit by bit) p5cr port 5 control reg. ff8ch (prohibit rmw) p57c p56c p55c p54c p53c p52c p51c p50c w 00000 0 0 0 0: in 1: out (i/o selected bit by bit) p6cr port 6 control reg. ff8eh (prohibit rmw) p67c p66c p65c p64c p63c p62c p61c p60c w 00000 0 0 0 0: in 1: out (i/o selected bit by bit) (3) timer/event counter control msb lsb symbol name address 7654 3210 treg0 8bit timer register 0 ff90h prohibit rmw w undefined treg1 8bit timer register 1 ff91h prohibit rmw w undefined treg2 8bit timer counter latch register 2 0ff92h r/w r : counter latch register 2, w : 8bit timer register 2 undefined treg3 8bit timer latch register 3 ff93h w r/w r : counter latch register 3, w : 8bit timer register 3 (2) i/o port control msb lsb symbol name address 76543 2 1 0
toshiba corporation 93 tmp90c400/401 tclk 8bit timer source clock control reg. 0ff94h t3clk1 t3clk0 t2clk1 t2clk0 t1clk1 t1clk0 t0clk1 t0clk0 r/w r/w r/w r/w 0000 0000 00 : to2trg 01 : ?1 10 : ?16 11 : ?256 00 : t12 01 : ?1 10 : ?16 11 : ?256 (8bit mode only) 00 : to0trg 01 : ?1 10 : ?16 11 : ?256 00 : t10 01 : ?1 10 : ?16 11 : ?256 (8bit mode only) tffcr 8bit timer flip-flop control reg ff95h latch3 latch3 tff1c1 tff1c0 tff1ie tff1is w w w r/w 11 0 0 0: latch (one shot) 00 : clear tff1 01 : set tff1 10 : invert tff1 11 : don? care 0 : invert disable 1 : invert enable 0 : invert by 8bit timer 0 1 : invert by 8bit timer 1 tmod 8bit timer mode reg. ff96h t32m1 t32m0 t10m1 t10m0 pwm01 pwm00 r/w r/w r/w 00 0000 00 : 8bit timer/counter 01 : 16bit timer/counter 10 : don? care 11 : don? care 00 : 8bit timer 01 : 16bit timer 10 : 8bit ppg 11 : 8bit pwm 00 : - 01 : 2 6 - 1 pwm period 10 : 2 7 - 1 11 : 2 8 - 1 trun 8bit timer/ serial channel baud rate control reg. ff97h brate1 brate0 prrun t3run t2run t1run t0run r/w r/w 0000 0000 00 : 300/150 bps 01 : 1200/600 10 : 4800/2400 11 : 19200/9600 prescaler & timer run/stop control 0 : stop & clear 1 : run (count up) (4) serial channel control msb lsb symbol name address 7 6 5 4 3210 scmod serial channel mode reg. ff99h tb8 fixed at ? rxe wu sm1 sm0 sc1 sc0 r/w undefined 0 0 0 0000 transmission bit-8 data in 9bit uart write ? 1 : receive enable 1 : wake up enable 00 : i/o interface 01 : uart 7bit 10 : uart 8bit 11 : uart 9bit 00 : to2trg 01 : br 10 : ? 11: br 1/2 u a r t sccr serial channel control register ff9ah rb8 oerr ferr r r (cleared to ??by reading) undefined 0 0 0 0 0 receiving bit 8 data 1: error overrun 1: error flaming (3) timer/event counter control msb lsb symbol name address 7654 3210
94 toshiba corporation tmp90c400/401 also refer to p3fr, trun register. note: br: baud rate generator scbuf serial channel buffer register ff9bh prohibit rmw rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 r (receiving)/w (transmission) undefined (5) interrupt control msb lsb symbol name address 7654 3210 intef interrupt enable mask reg. ff9ch ie0 iet0 iet1 iet2 iet3 ie1 ierx ietx r/w 0000 0000 1 : enable 0 : disable dmaef micro dma enable register ff9dh de0 det0 det1 det2 det3 de1 derx detx r/w 0 0 1 : enable 0 : disable irfr interrupt request flag & irf clear ff9eh irf0 irft0 irft1 irft2 irft3 irf1 irfrx irftx r (only irf clear code can be used to write) 0000 0000 1 : interrupt being requested (irf is cleared to ??by writing irf clear code) intmr int0 mode control reg. ff9fh edge r/w 0 0 : level 1 : - edge (4) serial channel control msb lsb symbol name address 7 6 5 4 3210
toshiba corporation 95 tmp90c400/401 (6) standby mode control msb lsb symbol name address 7654 3210 stbmod standby mode reg. ff8fh haltm1 haltm0 exf drive r/w rr/w 0 0 undefined 0 standby mode 00 : run mode 01 : stop mode 10 : idle1 mode 11 : idle2 mode invert each time exx instruction is executed 1 : to drive pin in stop mode
96 toshiba corporation tmp90c400/401 6. port section equivalent circuit diagram reading the circuit diagram basically, the gate singles written are the same as those used for the standard cmos logic ic [74hcxx] series. the dedicated signal is described below. stop: this signal becomes active ??when the hold mode setting register is set to the stop mode and the cpu executes the halt instruction. when the drive enable bit [drive] is set to ?? however, stp remains at ?? the input protection resistans ranges from several tens of ohms to several hundreds of ohms. po (ad0 ~ ad7), p1 (a8 ~ a15), p4, p6
toshiba corporation 97 tmp90c400/401 p20 ~ p23, p25, p5 p24 (nmi )
98 toshiba corporation tmp90c400/401 p26 (rd ), p27 (wr ) p30 ~ p33
toshiba corporation 99 tmp90c400/401 p34 ~ p37 clk x1, x2
100 toshiba corporation tmp90c400/401 ?a reset ale

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